During the manufacturing of integrated circuits, generally referred to as ICs, some method is required to test each individual electrical circuit on the IC to determine whether it meets the product requirements of functionality, signal timing, signal speed, power consumption, and thermal limits. Such IC testing is performed several times during the course of IC manufacture. Semiconductor substrates, generally known as wafers and generally made of silicon, are tested partway through the manufacturing process to determine whether it is economical to complete manufacture, or dispose of or recycle the silicon wafer. Finished silicon wafers are tested to determine which individual ICs are functional and thus should be packaged, versus which ICs are defective and should be discarded. Packaged ICs are tested to determine if damage has occurred during packaging operations, and whether the finished component is fast enough to meet specifications. Packaged ICs are also subjected to accelerated lifetime testing to determine the probable average lifetime of the IC, often referred to as the mean time to failure. Packaged ICs may be subjected to what is known as burn in, to determine which ICs have infancy failure problems. In all of the above noted situations, the IC must be connected to some sort of test system and functionally operated to determine if the IC is operational and within specifications.
It is known in the art to use computerized test systems to measure performance of IC circuits by means of what are known as test patterns. Test patterns consist of lines of computer code which direct the computerized test system to provide specified voltage and current levels to specified electrical input and power connections on the IC for specified periods of time. The test patterns also contain test system information as to the correct output voltage, current, and the timing to expect on specified output connections of the IC. In other words, test patterns consist of input stimuli and expected output results. The test patterns are developed and exercised on the ICs in an attempt to uncover manufacturing defects and reliability problems, as well as operating speed problems, design margin deficiencies, and operating window width problems. All of this testing is necessary to prevent electronic parts that do not meet specifications for speed, power consumption, and operational margins from being delivered to customers.
One of the goals of IC test patterns is to make sure that each circuit meets its clocking frequency requirements. This means looking for operational circuits that may have functionality problems at certain clocking frequencies due to specific signal paths within the IC design having speed critical timing problems. Thus, test patterns are designed to look for marginal design deficiencies that prevent proper circuit operation depending on the clock frequency used. Speed critical circuit paths are those parts of the IC design that have difficulty meeting all of the timing requirements at some specified clock frequency.
Most IC circuits have timing critical issues to one degree or another in some parts of their design. The faster the desired IC operational clock speed, the more likely it is, in general, for there to be serious timing requirements somewhere in the circuit. The maximum frequency or speed at which clocking of an IC can occur is determined by the implementation of the IC design's logic and circuit timing. For example, if the time it takes an electrical signal to propagate through a particular group of logic elements from one latch to another is close to the clock frequency, then variations in manufacturing or in circuit operating temperatures may cause slightly slower propagation and result in a failure of the IC due to the logic signal not arriving at the latch before the clock signal. Even if the signal propagation on a device is fast enough to beat the average specified clock signal, it may still result in a failure at a clock frequency that is higher than average but still within the specified range. Since higher frequency operation results in greater IC functional capability, there is always a desire within the industry to operate ICs at ever faster clock rates, thus increasing the sensitivity of the IC to the above noted speed critical timing problems.
In order to determine which parts of a circuit design have timing critical issues, it is possible to perform what is known as a design verification or a timing verification. A timing verification is a computer simulation of either the static or dynamic operation of the circuit design. This computer simulation is also known as a circuit model. The simulation predicts which parts of a particular design are likely to have timing critical issues. These critical circuit paths should be tested over the full specification range of values on each individual IC, in order to ensure that only ICs that meet the specification reach the customer. Typically, test patterns are generated to especially test the predicted speed critical paths, either manually or by automatic methods depending upon the type of electronic circuit. The test patterns may be used either during a simulation of the circuit function, or during testing of manufactured devices to determine circuit function under various conditions.
However, proving that the test patterns generated to test the function of suspect circuit paths actually work to uncover speed issues in the circuit design has been historically difficult. This is because it depends on the large number of possible different states that the IC may access and upon the many different input signal values. A change in state at the point of interest must still be observable to the outside world through a propagation path. In other words, how do you verify the operation of the test patterns that were generated, and what is your test coverage?
There are two methods known in the art to verify the timing of an IC design. The first known method to verify speed critical circuit paths is empirical electrical tests on the IC design after it has been manufactured in silicon, or other semiconductor material. The test patterns are typically used by a computer to functionally operate the IC at various high clock speeds to determine what clock rate induces failure. This method is not used very often because of the long lead times necessary to fabricate a specific circuit design in silicon, and because of the expense of fabricating ICs that may be a total or partial loss due to speed sensitive design faults.
The second method is either a static or a dynamic timing simulation of the circuit, with the circuit designer working with the simulation program to correct the IC design based on the simulation results. A static verifier, such as Zeist by Compaq, Pathmill by Synopsis, or Pearl by Cadence, is a patternless analysis of the circuit design looking for possible problems. A dynamic simulation program, such as SPICE by the University of California at Berkeley, is a pattern-based simulation of the circuit design which can be used to look for problems that are stimulated and observed by the test patterns. Static timing verification is becoming more popular since dynamic simulation is computationally expensive and prone to miss potential problems. This is known as inadequate pattern coverage. Dynamic timing verification methods are popular even though there is no method to ensure that all of the speed critical paths known to the IC designer will have a test pattern generated that can successfully test for a potential IC speed problem.
Timing simulation methods require that the circuit under test must have two features in order to demonstrate the validity of the test pattern, or test coverage. The first necessary feature is that the circuit design have adequate controllability. This means the circuit can be prompted to change state or to be stimulated to a changed state with the application of a new set of input signals.
The second necessary circuit feature to properly validate a test pattern is observability, or the ability to observe a change in electronic state within the circuit. Another term for these two features is COPs (Controllability Observability Points). COPs may be designed into a circuit at the circuit logic level, and the number of possible COPs will vary depending on the circuit design methodology, i.e., full custom, standard cell, gate array, or programable array.
There are two main methods known in the art to provide the test patterns for the proper testing of speed critical paths. The first method is known as ATPG or automatic test pattern generation. While the static simulation methods used to generate the ATPG test patterns are generally thought to be sufficient to ensure that speed critical issues are properly tested, it would be a benefit to have a method to verify or prove that the generated test pattern does accurately screen speed critical paths. ATPG also requires additional circuitry be placed on the silicon, which results in larger die sizes, more expense, and reduced circuit operating speeds. Further, industry experience shows that since the number of possible logical inputs to a speed critical path plus the inputs to the propagation path that leads to an observability point are too numerous to have confidence that all possible timing combinations are taken into account in the ATPG test pattern. In some cases, more than half of the speed critical paths have been found to not be properly covered by the test patterns. For example, a test pattern that does test for speed problems in a critical circuit may simply not have every input to the propagation circuit enabled, and thus not see the speed sensitive problem.
The second method known in the art to provide test patterns is known as ad-hoc manual generation. This method requires the intensive manual efforts of the circuit designer and test engineer to attempt to write test patterns to properly test the known and suspected speed critical paths. In the worst case, the COPs are the input and output electrical connections of the IC itself. This method is more expensive than ATPG and suffers from what is known as a test coverage problem, in that there is no method to ensure that all of the suspected or known speed critical circuits are properly tested by the manually generated patterns.
The timing and speed issues are not the only problems in test pattern verification. Similar situations exist whenever an internal node of a circuit is not directly detectable to the designer or user. Any type of problem that can occur inside the logic of an electronic system may not be detectable by the designer because of the additional circuit elements needed to propagate the logic to a point where the signal is detectable. Thus, there exists a problem in the art of efficiently evaluating test patterns to ensure that they do indeed accurately test the speed critical paths for the IC or other electronic device.